1. Field of the Invention
The present invention relates to a semiconductor memory device using a ferroelectric film, and more specifically to a semiconductor memory device which has a structure suitable for miniaturization, and its manufacturing method.
2. Description of the Related Art
Upon progress of miniaturization to realize high integration, a semiconductor memory device, such as a dynamic random access memory (DRAM), has employed a three-dimensional structure. FIGS. 44A, 44B show an example of a conventional trench type ferroelectric random access memory (FeRAM) which is one of three-dimensional structures. The drawings are illustrated to explain sectional structures. FIG. 44A shows a single trench type FeRAM, and FIG. 44B shows a serially connected trench type FeRAM. As shown in FIGS. 44A, 44B, the trench type FeRAM comprises a metal oxide semiconductor (MOS) transistor 40, and a trench ferroelectric capacitor 50 formed in one source/drain 46a of the MOS transistor and constituted of a lower electrode 56, a ferroelectric film 58, and an upper electrode 60. The upper electrode 60 of the capacitor is connected to a plate line 90 through a first contact plug 86. Additionally, in the serially connected trench type FeRAM shown in FIG. 44B, a plate line 90b is connected to the other source/drain 46b of the MOS transistor through a second contact plug 84. In this trench type FeRAM, since the contact plug 86 connected to the plate line 90 should be formed from the upper electrode 60 of the capacitor 50, this portion needs (A) a margin for processing, consequently, it imposes a limitation on miniaturization. Further, in the serially connected trench type FeRAM shown in FIG. 44B, as to trench capacitors 50a, 50b formed in the same source/drain 46a, their lower electrodes 56a, 56b are commonly connected, and their upper electrodes 60a, 60b are connected to different plate lines 90a, 90b. Securing of (B) a space between the plate lines 90a, 90b is also an obstacle to miniaturization.
FIGS. 45A, 45B show an example of a stack type FeRAM of a conventional structure which is another three-dimensional structure. The drawings are illustrated to explain sectional structures. FIG. 45A shows a single stack type FeRAM, and FIG. 45B shows a serially connected stack type FeRAM. As shown in FIGS. 45A, 45B, the stack type FeRAM comprises a MOS transistor 40, and a stacked ferroelectric capacitor 51 constituted of a columnar lower electrode 56, a ferroelectric film 58, and an upper electrode 60 formed on a first contact plug 82 on one source/drain 46a of the MOS transistor 40. The upper electrode 60 is connected to a plate line 90 through a third contact plug 86. Additionally, in the serially connected stack type FeRAM shown in FIG. 45B, a plate line 90b is connected to the other source/drain 46b of the MOS transistor 40 through a second contact plug 84. In this stack type FeRAM, miniaturization causes problems due to following micro-fabrication itself. For example, (B) a space between separate plate lines 90a, 90b, (C) alignment of the first contact plug 82 to the stacked capacitor 51, (D) a processing margin between adjacent capacitors 51, (E) etching processing of the columnar lower electrode 56, (F) processing of the contact plug 86 for connecting the plate line 90b formed above the capacitor 51 to the source/drain 46b, and the like can be cited as problems.
Furthermore, Jpn. Pat. Appln. KOKAI Publication No. 10-303396 discloses yet another FeRAM with different three-dimensional structure. The FeRAM has a flat capacitor with a ferroelectric film to suppress its characteristic deterioration caused by its three-dimensional structure. The capacitor constituted of epitaxially grown layers of a first electrode 104, a ferroelectric film 105, and a second electrode 106 is formed on a silicon wafer 101. A silicon-on-insulator (SOI) layer 109 is formed on the wafer having the capacitor via an insulator 110. A MOS transistor is formed on the SOI layer 109. The first electrode 104 of the capacitor also has a function of a plate line. This structure is suitable for miniaturization because an area below the MOS transistor can be used for the capacitor. However, there are various problems described below. The capacitor is formed on the silicon wafer 101 using an epitaxial growth. However, materials of the components of the capacitor are different from silicon. The epitaxial growth that uses such different kinds of materials, i.e., hetero-epitaxial growth, is a very sophisticated technology. To execute high-quality epitaxial growth without introducing crystal defects and so on, there are restrictions on materials to be used. In addition, a manufacturing process is complex since the SOI structure is employed.
As described above, a semiconductor device including a ferroelectric random access memory having a structure suitable for miniaturization and easy to manufacture, and having less restrictions on materials to be used, and its manufacturing method is required.